Status
Current snapshot of the project. Updated to reflect actual state.
Current Status
InferASIC is in an early stage: concept, design, and software emulation. There is no production hardware, no physical chip, no physical board, and no launched product. Active work is software emulation, system design, and hardware feasibility investigation. The project is active but pre-product.
Active Workstreams
- Software emulation of the inference pipeline and data flow
- Architecture design and tradeoff analysis
- Runtime and orchestration exploration
- Hardware feasibility and technology path investigation
Development Roadmap
Phases are indicative. Order and timing may change as the work progresses.
Phase 1: Concept and system design
Define high-level architecture, inference model, and design principles. In progress.
Phase 2: Software emulation and pipeline validation
Emulate the target pipeline and data flow in software to validate the approach before hardware commitment.
Phase 3: Hardware architecture refinement
Refine the hardware architecture based on emulation results and feasibility work. No RTL or tape-out in this phase.
Phase 4: Prototype planning
Plan for prototype hardware when the design is sufficiently mature. Not started.
Phase 5: Future card development
Development of inference cards and deployment path. Timeline and scope to be determined.